1. Field of the Invention
The present invention relates to a successive approximation analog-to-digital converter, and particularly to such a converter in which a non-binary sequence is employed, and which does not require precise components.
2. Description of the Prior Art
A successive approximation analog-to-digital (A/D) converter provides a digital output which indicates the magnitude of an unknown analog input signal. The output may be a decimal number such as "4.25" or a binary number such as "10.01" which signifies some multiplier times a standard unit such as the "volt".
A convention successive approximation A/D converter employs a digital-to-analog converter (DAC) in a feedback loop with a comparator and a logic circuit referred to as a "successive approximation register". In the standard system, a binary sequence is employed. Initially the most significant binary bit (MSB) is set to one, and all lower bits are set to zero. The DAC then produces an analog voltage corresponding to the value of that most significant bit. For example, in a 10-bit system, the DAC initially would produce a voltage of 2.sup.9 =512 volts. If this voltage is less than the analog input, the MSB is left at one. If the DAC output is greater than the input, the bit is set to zero.
The successive approximation register then moves on to the bit of next lower significance. This bit is set to one, and the resultant DAC output again is compared to the unknown analog input. If the DAC output is less than the input, this bit is left at one; if not, the bit is set to zero. The process is repeated successively for all bits. At the completion of the conversion, those bits left in the one state produce an output voltage from the DAC which should match the analog input to within .+-.1/2 LSB. Performing an "n" bit conversion requires only "n" trials, making the technique capable of high speed conversion.
In the conventional successive approximation converter employing a binary sequence, the digital-to-analog converter uses an impedance network in which the elements correspond to values of the binary sequence. For example, the DAC may employ a set of resistors which are selected to produce voltages or currents having values of 512, 256, 128, 64, 32, 16, 8, 4, 2 and 1.
With this embodiment, during the successive approximation operation, the resistor or other impedance element having the value 512 initially is switched into the circuit. The comparator then compares the resultant current or voltage with the analog input. If, for example, the unknown signal is 328.3 volts, the comparator determines that this value is less than 512 volts produced by the DAC. As a result, the MSB is reset to zero, and the next bit is set to one. The analog input again is compared to the DAC output, which now is 256 volts. Since the unknown value (328.3 volts) is greater than 256 volts, this bit is kept in, and the next bit (having the binary weight 128) now is switched to one. Since the analog value is less than the sum of 256 plus 128, the bit corresponding to 128 is taken out and the next successive bit (having a value of 64) is put in. The process is repeated for all bits. At the end of the conversion, the bits having the weights of 256, 64 and 8 will remain set to one, so that the binary output code is 0101001000, this being the binary representation of 328. This system can only represent 328.3 (the unknown value) to an accuracy of 328, i.e., to within the value "1" of the least significant bit (LSB).
To ensure that this system gives a correct representation of the unknown analog input, two requirements must be met. First, each DAC element in the series must be accurate in value to a degree which is less than magnitude of the smallest element in the series. In the above example, each resistor or other impedance element must be accurate to within 1 unit. Secondly, the detector which compares the value corresponding to the sum of the inserted elements with the unknown value must be given enough time to register differences which are smaller than the magnitude of the smallest element. In practice, most comparators require a certain time for transient responses to settle out before a valid reading can be obtained. The more fine the requirement for accuracy, in general, the longer is the time required for the settling of transients. This settling time limits the speed at which accurate conversions can be made.
With regard to the first of these requirements, it is generally difficult to manufacture a resistor or other impedance element so as to have the precise desired value. However, since such precision is necessary to ensure that the DAC output is of the exact value at each step, the cost of fabrication of the converter is increased. On the other hand, it is usually easier and cheaper to measure an element accurately after it is manufactured than to manufacture it to a precise, certain value. An object of the present invention is to provide an analog-to-digital converter which utilizes components that need not be manufactured to precise values. The present invention utilizes DAC components which need not have specific values, so long as the actual value of each component is exactly known. Since this simplifies the manufacturing requirements, lower cost is achieved.
The second requirement listed above results in part because in the binary series (1, 2, 4, 8, 16, 32, . . . ) the sum of the first n elements is equal to the (n+1).sup.th element less one. For examnple: EQU 1+2+4+8+16=32-1
Thus, in a successive approximation A/D converter using a binary series, if an error occurs in the comparison between the DAC output and the unknown input for a certain DAC step, the error can not be compensated for in later steps. For example, suppose that the unknown analog input has a value of 17. Suppose further that when the DAC output is supposed to be "16" an error occurs, and the comparator indicates that the unknown signal is less than the DAC output. This error could result because the impedance element in the DAC was of incorrect value, or more likely, because of erroneous comparator operation due, e.g., to insufficient settling time to eliminate transient responses. As a result, the "16" bit will be set to zero. The sum of the remaining bits (having binary weights 1, 2, 4 and 8) is 15, which is less than the actual unknown value of 17. As a result, even though these four bits all will be set to one, the resultant converter digital output will have a value of 15 (i.e., binary 01111), which is an incorrect representation of the true analog input value 17.
Another object of the present invention is to provide a successive approximation A/D converter which does not employ a binary series, and in which an error in comparison at one step of the DAC output can be compensated for during subsequent DAC output steps. By employing a non-binary sequence in which the sum of the preceding series elements exceeds the value of the next element, the comparator accuracy requirements are substantially reduced. This leads to another object of the present invention, which is to provide an A/D analog converter in which the comparator accuracy requirements are reduced, and hence in which a shorter time is required for the settling of transients to a degree sufficient to obtain conversions of the desired resolution. Thus a corresponding objective of the present invention is to provide a successive approximation A/D converter having a shorter conversion time than prior art units of like precision, or having greater measurement resolution (e.g., more binary bits in the converted output) than a prior art converter operating with the same conversion time interval.